module dtackgen(clk, i, dtack, as);
input	clk, as;
input	[2:0]i;
output	dtack;
reg	[2:0]counter;

assign dtack = counter[0] | counter[1] | counter[2];

always@(posedge clk)
begin
	if(as)
		counter <= i;
	else	if(counter > 0)
		counter <= counter - 1;
end
endmodule